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| preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 2000 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com cdb4923 CDB49300 evaluation board for cs4923/cs49300 families features cdb4923 demonstrates 5.1 channel decode capability of the cs4923 family CDB49300 demonstrates 5.1 channel decode capability of cs49300 family 6 discrete analog outputs driven by cs4340 dacs 4 s/pdif optical outputs accepts analog input, s/pdif digital input, bursty compressed data discrete pll which can provide multiple sampling frequencies interfaces to a personal computer through the parallel port stake headers provide convenient location for direct wiring to control signals from off- board microcontroller interface for external memory card digital and analog patch areas description the cdb4923 and CDB49300 customer development boards provide the means to fully evaluate the cs4923/4/5/6/7/8 and cs49300 family of audio decod- ers. compressed data can be delivered in iec61937 format via the s/pdif port and in bursty mode via the pc interface. pcm data can be accepted through the digital input connectors or from the on-board adc. six chan- nels of audio are provided on the six analog outputs and on three optical s/pdif transmitters. clkin for the dsp can be derived either from the on-board oscillator or the external pll. mclk can be extracted from incoming s/pdif streams, generated with the external pll, or mastered by the audio decoder. the cdb4923/300 incorporates a crystal multichannel audio decoder, the cs4340 24-bit audio d/a converter, the cs8414 digital audio interface receiver, the cs8404a digital audio interface transmitter, and the cs5334 20-bit stereo a/d converter. ordering information cdb4923 evaluation board CDB49300 evaluation board i analog output stereo analog in digital output digital input control interface patch area reset cs8414 pll +3.3v +2.5v cs492x cs493xx osc pld cs8404a cs8404a cs8404a cs4340 cs4340 cs4340 cs5334 digital sound processing crystal ? ? jan ?00 ds262db2
cdb4923 CDB49300 2 ds262db2 table of contents 1. cdb4923 vs. CDB49300 ...................................................................................................... ... 5 1.1 dsp power ................................................................................................................. ....... 5 1.2 dsp pll filter ............................................................................................................ ....... 5 2. operation ................................................................................................................. ............ 5 2.1 power requirements ........................................................................................................ .6 2.2 dolby? considerations ..................................................................................................... ... 7 3. digital signal processor ............................................................................................. 7 3.1 control signals ........................................................................................................... ........ 7 3.2 external memory ........................................................................................................... ..... 8 4. control ................................................................................................................... .............. 8 5. data selection ............................................................................................................ ....... 9 5.1 provided mode ............................................................................................................. .... 10 5.1.1 control ................................................................................................................. 10 5.1.2 data .................................................................................................................... .10 5.1.3 audio clocking .................................................................................................... 12 5.2 external mode ............................................................................................................. ..... 12 6. clocking .................................................................................................................. ........... 14 6.1 dsp clock ................................................................................................................. ....... 14 6.2 mclk ...................................................................................................................... ......... 15 6.3 lrclk and sclk ............................................................................................................ 15 7. input ..................................................................................................................... ................. 16 7.1 analog input .............................................................................................................. ....... 16 7.2 digital input ............................................................................................................. ......... 16 8. output .................................................................................................................... .............. 17 8.1 analog output ............................................................................................................. ..... 17 8.2 analog output protection circuitry ................................................................................... 17 8.3 digital output ............................................................................................................ ....... 17 9. appendix a: schematics ...................................................................................... 18 10. appendix d: bill of materials .................................................................................. 34 11. appendix e: external memory schematics ..................................................... 37 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/ dolby is a registered trademark of dolby laboratories licensing corporation dts is a registered trademark of dts, inc. preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best effort s to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provi d ed ? as is ? without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. for the use of this information, nor for inf ringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, tradem arks, or trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electron ic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc. items from any cirrus logic website or disk may be printed for use by the user. however, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form o r by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc.furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. the names of products of cirrus logic, inc. or ot her vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. a list of cirrus logic, inc. trade- marks and service marks can be found at http://www.cirrus.com. cdb4923 CDB49300 ds262db2 3 12. appendix f: board control software ................................................................. 39 13. appendix g: ic component listing by function ................................................. 42 13.1 power ..................................................................................................................... ........ 42 13.2 reset ..................................................................................................................... ......... 42 13.3 clocking.................................................................................................................. ........ 42 13.4 signal routing/level conversion ................................................................................... 42 13.5 dsp ....................................................................................................................... ......... 42 13.6 input..................................................................................................................... ........... 42 13.7 output.................................................................................................................... ......... 42 14. appendix h: jumpers listed by function ............................................................. 43 14.1 audio input jumpers....................................................................................................... 43 14.2 audio output jumpers .................................................................................................... 43 14.3 dsp jumpers ............................................................................................................... .. 43 14.4 power jumpers............................................................................................................. .. 44 14.5 system clocking jumpers .............................................................................................. 44 15. appendix i: jumpers listed by number .................................................................. 46 16. appendix j: switch summary ..................................................................................... 47 list of figures figure 1. external memory example.............................................................................................. .9 figure 2. cdb4923/300 data paths.............................................................................................. 1 1 figure 3. audio clocking ....................................................................................................... ........ 12 figure 4. audio clocking ....................................................................................................... ........ 12 figure 4. cs492x/cs493xx....................................................................................................... .... 18 figure 5. system power......................................................................................................... ....... 19 figure 6. pc interface ......................................................................................................... .......... 20 figure 7. control logic........................................................................................................ .......... 21 figure 8. clocking ............................................................................................................. ............ 22 figure 9. analog input......................................................................................................... .......... 23 figure 10. digital input ....................................................................................................... ........... 24 figure 11. d/a converters ...................................................................................................... ...... 25 figure 12. analog output ....................................................................................................... ....... 26 figure 13. digital output ...................................................................................................... ......... 27 figure 14. top layer........................................................................................................... .......... 28 figure 15. bottom layer........................................................................................................ ........ 29 figure 16. sstop............................................................................................................... .......... 30 figure 17. asystop ............................................................................................................. ....... 31 figure 18. layer 2 ............................................................................................................. ............ 32 figure 19. layer 3 ............................................................................................................. ............ 33 figure 20. crd4923-mem schematic.......................................................................................... 37 figure 21. CDB49300-mem schematic ........................................................................................ 38 cdb4923 CDB49300 4 ds262db2 list of tables table 1. cs492x/cs493xx host interface mode selection............................................................. 8 table 2. data selection modes (pld version ab-x)..................................................................... 10 table 3. provided data selection modes (pld version ab-x) ................................................. 11 table 4. digital audio sources ................................................................................................. ..... 11 table 5. clocking descriptions................................................................................................. ..... 12 table 6. dsp pins tri-stated by u11 in pld mode 0 ................................................................... 13 table 7. dsp pins tri-stated by u11 in pld mode 1 ................................................................... 13 table 8. clocking descriptions................................................................................................. ..... 13 table 9. data selection modes (switch s3, pld version ab-x) .................................................. 14 table 10. external data selection modes (pld version ab-x) .............................................. 14 table 11. board clocking configurations (j37)............................................................................. 14 table 12. pclk configurations.................................................................................................. ... 15 table 13. audio frequency selection (j58) .................................................................................. 15 table 14. cs5334 digital output formats (s4)............................................................................. 16 table 15. digital output format settings for cs8414 (s1)............................................................ 16 table 16. cs4340 digital input formats (s4) ............................................................................... 17 table 17. digital input format settings for cs8404a (s2) ............................................................ 17 table 18. cs492x/cs493xx host interface mode selection......................................................... 47 table 19. cs5334 digital output formats (s4)............................................................................. 47 table 20. cs4340 digital input formats (s4) ............................................................................... 47 table 21. digital output format settings for cs8414 (s1)............................................................ 47 table 22. pclk configurations.................................................................................................. ... 48 table 23. digital input format settings for cs8404a (s2) ............................................................ 48 table 24. data selection modes (switch s3, pld version ab-x) ................................................ 48 cdb4923 CDB49300 ds262db2 5 1. cdb4923 vs. CDB49300 the cdb4923 and CDB49300 are two customer development boards built from a single platform - the cdb4923/300. this development board replac- es the cdb4923 rev. a and rev. b. although the cdb4923/CDB49300 boards look very similar, it is important to be aware that when shipped from the factory, the cdb4923 is config- ured for only the cs4923 family of audio decoders and the CDB49300 is configured only for the cs49300 family of audio decoders. the features distinguishing the two boards are the following: ? dsp power setting dsp pll filter topology 1.1 dsp power the cs4923 family is designed to operate with a core voltage of +3.3 v, and the cdb4923 is shipped with the dsp power jumper in the +3.3 v position. the cs49300 family is designed to oper- ate with a core voltage of +2.5 v, and the CDB49300 is shipped with the dsp power jumper in the +2.5 v position. attempting to use an audio decoder on the wrong board (e.g., cs49300 on a cdb4923) can cause unpredictable results and damage the decoder. 1.2 dsp pll filter the pll of the cs4923 is different than that of the cs49300. consequently, the optimized external pll filters for each family of audio decoders is dif- ferent. the cdb4923 is optimized for the cs4923 family and the CDB49300 is optimized for the cs49300 family. attempting to use an audio de- coder on the wrong board (e.g., cs49300 on a cdb4923) can cause unpredictable results. specifically, the relevant pll filter components for the cdb4923 are: r246 = 0 ? c155 = 0.22 f the relevant pll filter components for the CDB49300 are: r246 = 33 k ? c155 = 0.22 f c113 = 0.01 f although the boards are tailored for one specific family of audio decoders, the operation of the cdb4923 and CDB49300 is effectively the same. this document will generically refer to the cdb4923/300 except in those instances where there is a difference between the boards. 2. operation the cdb4923/300 is designed to allow full evalu- ation of the cs4923 family and cs49300 family of audio dsps. the members of each audio decoder family are electrically equivalent, so it is possible to use any member of the cs4923 family in the cdb4923 and any member of the cs49300 family in the CDB49300. in the context of this document, cs492x should be interpreted as any member of the cs4923 family and cs493xx should be understood to be any member of the cs49300 family. the cdb4923/300 is composed of 8 distinct re- gions: dsp, control interface, control logic, clocks, analog i/o, digital i/o, patch area, and power. each board region has a number of compo- nents and will be briefly discussed below. a more thorough description of each will be given in dedi- cated sections of this document which can be quickly located in the table of contents. the dsp section includes the audio decoder (cs492x multichannel audio decoder or cs493xx universal audio decoder) under evaluation, jump- ers for controlling dsp power and dsp configura- tion pins, and stake headers which provide access to all relevant dsp pins. the jumpers allow the user to select between +2.5 v or +3.3 v on the dsp power pins (pre-configured at the factory for the cdb4923 CDB49300 6 ds262db2 proper voltage), configure the audio decoder for different host communication modes and select the clock source for the dsp (internal pll or external clock). the stake headers provide a convenient lo- cation for probing signal values and also serve as the interface to the crd4923-mem (for use with cs492x only) or CDB49300-mem (for use with the cs493xx only) external memory expander cards. the control interface of the cdb4923/300 is com- posed of a 25 pin connector designed to accept a parallel port cable, a programmable logic device (pld), and two ttl buffers designed to buffer the sixteen signal lines coming from the pc. using the software provided with the demonstration board, the user can download code to the dsp, configure the application code running on the dsp, perform a reset of the dsp, and deliver compressed audio files to the dsp. an additional control interface is provided on the j11 and j12 stake headers when the pld is placed into an external interface mode as described in data selection . the majority of the control logic for this board is found in the pld. the pld latches all signals com- ing from the parallel port interface, performs all i/o routing on the board, and provides level conversion from +5 v to +3.3 v/+2.5 v depending on the set- ting of the i/o power jumper (j63) for the pld. a dip switch is used to control different data/clock routing configurations. there is also an external re- set chip (max708) which is responsible for system reset at power-up and when the digital power be- gins to fail. the sources for the main dsp clock on the cdb4923/300 are the oscillator and the external pll. when the oscillator is chosen, the main dsp clock frequency can be either the 27 mhz or 12.288 mhz oscillator provided with the board. when properly configured the external pll can provide a processor clock frequency ranging from 33 mhz to 81 mhz. when the external pll is used for the dsp processor clock, it can also be used to master the system oversampling clock, mclk. the cdb4923/300 features six channels of analog output provided by three cs4340 dacs. the out- puts are provide a 3.5 v pp signal, and each output has protection circuitry to protect against speaker ?popping?. a dip switch is provided for changing the data format accepted by the cs4340. there is a stereo analog input on the cdb4923/300 which is designed to interface to line levels of up to 2v rms . the analog to digital conversion is per- formed by the cs5334. a dip switch is provided for changing the format of the audio data provided by the cs5334. input and output ports are provided for s/pdif dig- ital audio streams (iec60958 and iec61937). an incoming s/pdif stream can be supplied either with an optical cable or coaxial cable. the s/pdif outputs of the cdb4923/300 are all optical. the in- formation from the audata0-2 pins of the cs492x are transmitted on aout_dig0-2 using digital audio interface transmitters (cs8404a). optical output j43 is connected directly to the s/pdif transmitter of the dsp. dip switches are provided for changing the serial audio format of the data provided by the cs8414 and the data accepted by the cs8404a. the cdb4923/300 provides both analog and digi- tal patch areas. the digital patch area provides ac- cess to both +5 v and dsp power (voltage of the cs492x/cs493xx core). these patch areas are very useful when prototyping circuit modifications. they can also be used as a place to connect signal buffers when using the cdb4923/300 in an exter- nal interface mode. 2.1 power requirements this board is composed of about 75% digital logic which is fed by the +5 v power supply. since the cs492x is a +3.3 v part and the cs493xx is a +2.5 v part, there are also +3.3 v and +2.5 v volt- cdb4923 CDB49300 ds262db2 7 age regulators on the board (u8 and u27) which are used to power the dsp and the i/o pads of the pld (u11). the +12 v and -12 v supplies are used to power the input buffers on the analog side of the board. the power section of the cdb4923/300 can be found in figure 5. the cdb4923/300 requires a +5 v input on j23 and a digital ground connected to j24 in order to power the digital section of the board. the analog portion requires a +12 v supply on binding post j21, -12 v on j57, and analog ground connected to j22. 2.2 dolby ? it should be noted by the system designer that addi- tional circuitry may be required in order to obtain dolby certification (e.g., analog bass manage- ment). system requirements are dependent upon the nature of the end product and which group of dolby certification is required. the designer should consult the dolby licensee information manual and contact dolby laboratories to deter- mine exactly what is required to meet dolby spec- ifications for a particular system. 3. digital signal processor the cs492x/cs493xx (u1) must be downloaded with application code and configured for operation each time that it is powered up. each time the de- coder needs to be reconfigured, the host must send hardware configuration and application configura- tion messages to the dsp. a complete description of the software applications and their messaging protocol can be found in application notes an120- an123, an140 for the cs492x and an161- an163 for the cs493xx. please note that this document and all other docu- mentation pertaining to the cs492x family of de- coders can be found at the following website: http://www.cirrus.com/products/overviews/cs4923.html this document and all other documentation per- taining to the cs493xx family of decoders can be found at the following website: http://www.cirrus.com/products/overviews/cs49300.html as the focus of the board, the cs492x/cs493xx performs all processing of digital audio. the dsp section of the board is illustrated in figure 4. the cs492x/cs493xx can be fed compressed data or linear pcm from various sources. however, it should be noted that each load of application soft- ware for the dsp is designed to process a specific data type, e.g. dts ? application code does not process linear pcm. please reference the appropri- ate software application note (i.e. an120-an123, an140 or an161-an163) to determine which hardware configurations and audio data types are supported. 3.1 control signals the host interface to the dsp, which allows code download and other communication, can be access- ed through the parallel port interface (j29) or by placing the control pld into an external interface mode. in the external interface mode the user can drive the signal pins of the dsp by tapping into the signals present on headers j11 and j12. more infor- mation on selecting the host control mode can be found in data selection . the host interface mode of the dsp is selected at the rising edge of reset and is programmable. the communication mode is determined by the states of the rd , wr , and psel pins when the dsp comes out of reset, as described in the cs4923/4/5/6/7/8/9 datasheet and the cs49300 datasheet. each mode is described in the cs4923/4/5/6/7/8/9 hardware us- er?s guide (an115) and the cs49300 datasheet. there are six jumpers used to directly control the cs492x/cs493xx. jumpers j2 (wr ), j3 (rd ), and j62 (psel) are used to select the host interface mode for the cs492x/cs493xx. table 1 lists the jumper settings required for all four host interface modes. note that the cdb4923/300 requires cdb4923 CDB49300 8 ds262db2 psel==1 when configuring for i 2 c mode because psel and scdio are multiplexed onto the same pin. two of the dsp jumpers are designed to act as cur- rent measurement points for the cs492x/cs493xx. jumper j59 is the analog current measurement point, and it must be installed for the pll to func- tion. jumper j60 is the digital current measurement point, and it must be installed in order to supply power to the digital logic of the cs492x/cs493xx. jumper j1 is the clock selection jumper. when j1 is in the ?clkin? position, the clock present on pin 30 of the dsp (clkin) will drive the internal dsp clocks directly. when j1 is in the ?pll? position, the clock present at pin 30 is used as the reference clock for the cs492x/cs493xx internal pll. the frequency required for the reference clock when using the internal pll is application code depen- dent, so the relevant application code user ? s guide should be consulted to determine which frequency to provide. 3.2 external memory some cdb4923/300 boards may be shipped with an external memory board. there two different ex- ternal memory boards available: crd4923-mem - external rom for cs492x CDB49300-mem - external rom and ram for cs493xx the cs492x requires an external rom for auto- boot, and the cs4926 requires an external rom when processing dts audio streams. the crd4923-mem external memory board is tailored for the cdb4923. the schematic for crd4923- mem can be found in figure 20. the cs493xx family has integrated dts tables, so a rom is required only for autoboot. the cs493xx also has a static ram interface. the CDB49300-mem external memory board is tai- lored for the CDB49300. the CDB49300-mem schematic can be found in figure 21. the cdb4923/300 has been designed to interface to both the crd4923-mem and CDB49300-mem daughter boards. the card plugs directly on to j11 oriented such that the cs492x/cs493xx is not cov- ered, as shown in figure 1. please consult the memory map associated with the revision of rom installed in the memory card to determine which code loads are available. the memory map can be found in the ? .fmt ? file found on the included floppy. 4. control control of the cs492x/cs493xx can be accom- plished in two ways. the cdb4923/300 is shipped with a parallel computer cable which can be at- tached to the parallel port (lpt1, lpt2, or lpt3) of any computer which has a windows or dos based operating system. the parallel port (j29) in- terface circuitry is illustrated in figure 6. the soft- ware shipped with the cdb4923/300 is based on command-line programs which must be executed from a dos prompt. the cdb4923/300 software provides the means to reset the cs492x/cs493xx, write control data to the dsp, read control data from the dsp, and deliver compressed audio. a de- tailed description of the software can be found in appendix f: board control software . alternatively, the board can be put into a mode which tri-states all connections between the pld and the dsp (full external mode), or a mode that tri-states the control lines (external control mode) of the cs492x/cs493xx while still driving the data rd j3 wr j2 psel j62 host interface mode 011 serial i 2 c (psel==scdio) 10x serial spi 1 1 0 8-bit intel 1 1 1 8-bit motorola table 1. cs492x/cs493xx host interface mode selection cdb4923 CDB49300 ds262db2 9 input ports of the dsp. these configuration allows the user to drive signals on stake headers j11 and j12 in order to operate the dsp as if it were part of an embedded system. the user is responsible for providing the appropriate clocking signals, control signals, and data signals to the dsp in full external mode, but the user only provides control signals in exernal control mode. in the external modes the audio output of the dsp still drives the on-board dacs and digital transmit- ters thus allowing the user to access the audio on the analog and digital output connectors provided by the cdb4923/300. the stake headers j11 and j12 can be found in figure 4. all on-board clocks and data lines are routed through the pld (u11) in order to provide maxi- mum flexibility in the evaluation of different sys- tem configurations. the pld will perform all +5 v to +3.3 v/+2.5 v conversions between the dsp and the +5 v parts with which it interacts by con- figuring the i/o power jumper (j63). the system can also be configured in an external interface de- scribed above. the external modes are detailed in data selection . all pld modes are selected using dip switch s3. the pld (u11) and switch s3 are shown in figure 7. a specialized ic (u12), the max708, has been in- cluded on the cdb4923/300 in order to generate a system reset at power-up, when the digital power begins to fail, and when the system reset button (sw1) is depressed. this chip helps to insure con- sistent operation on the board by providing a 200 ms reset pulse whenever activated. 5. data selection data selection on the cdb4923/300 refers to the routing of audio data, audio clocks, control data, and control clocks. because the pld plays such a crucial role in determining the routing and control scheme, each data selection mode is also referred to as a ? pld mode. ? it is important to note that table 2, the pld mode table, is based directly upon the version of the control pld (u11) used on each par- ticular board. each pld has a specific revision code printed on its label. if your pld version dif- fers from the one described in this document, con- tact the factory to determine which feature set is provided with your board. analog output stereo analog in digital output digital input control interface patch area reset cs8414 pll +3.3v +2.5v cs492x cs493xx osc pld cs8404a cs8404a cs8404a cs4340 cs4340 cs4340 cs5334 crd4923-mem CDB49300-mem figure 1. external memory example cdb4923 CDB49300 10 ds262db2 the two major pld modes for the cdb4923/300 are the provided resource mode and the ex- ternal interface mode. when a provided mode is chosen all clocks are provided by the dem- onstration board, all audio data passes through the pld, and the dsp is controlled by the pc parallel port interface. the external interface modes allow the user to drive the audio data and control pins of the dsp directly by wire-wrapping to stake headers j11 and j12, bypassing the control pld. it should be noted that there are two variants of the external interface mode. one external mode provides direct access to all control and audio data input pins of the cs492x/cs493xx, and the second external mode allows the user to drive the control signals of the cs492x/cs493xx while audio data still comes from the cdb4923/300. the dip switch s3 is used to choose the different routing schemes, and can be found in the control schematic of figure 7. table 2 provides a general overview of the available pld modes. 5.1 provided mode when the user has chosen a provided resource mode, the pld mode determines the source of au- dio data for the two data pins of the dsp (cmp- dat ? pin 27 and sdatan1 ? pin 22) and the source of the system's oversampling clock (mclk). table 3 lists the routing configurations for each of the provided data selection modes. 5.1.1 control as mentioned earlier, when a provided mode has been selected, all control of the cdb4923/300 is accomplished using the parallel port (j29). a floppy disk is included with the cdb4923/300 which contains the control software described in appendix f: board control software . 5.1.2 data all of the data selection modes shown in table 3 imply pc control. in table 4, a brief description is given for each data source listed in table 3. the general data flow of the system is illustrated in figure 2. a data path is shown for each of the modes listed in table 3. pld mode data_sel2 data_sel1 data_sel0 audio data, control, and clocks control source 0 lo lo lo external j11 1 lo lo hi external control only j11 2 lo hi lo provided pc 3 lo hi hi provided pc 4 hi lo lo provided pc 5 hi lo hi provided pc 6 hi hi lo reserved 7 hi hi hi reserved note : because each mode of the data selection switch (s3) sets up a different hardware configuration, clock and data lines may be momentarily directed to many different destinations during mode changes. without the proper initialization process after a reconfiguration, strange behavior may be observed. the recom- mended procedure for performing changes to the routing configuration is to first generate a board reset using the board reset switch (sw1). the cs492x/cs493xx will then require a soft reset ("cdb30rst.exe -s" which performs a hardware reset and then sends the soft reset message 0x000001) and the proper hardware and application configuration messages for the new mode. a thor- ough description of soft reset, hardware configuration, and application configuration can be found in the software application notes an115, an120-123, an140 or an161-163. table 2. data selection modes (pld version ab-x) cdb4923 CDB49300 ds262db2 11 cs5334 cs8414 data parallel compressed data stereo pcm cs8414 cs4340 cs4340 cs4340 cs8404a cs8404a cs8404a cdi dai pcm out xmt958 xmt958 cs492x cs493x x figure 2. cdb4923/300 data paths pld mode data_sel2 data_sel1 data_sel0 cs492x/cs493xx cmpdat cs492x/cs493xx sdatan1 mclk source 2lo hi lo pc a/d ? cs5334 dsp 3lo hi his/pdif ? cs8414 s/pdif ? cs8414 cs8414 4hi lo los/pdif ? cs8414 a/d ? cs5334 cs8414 5hi lo hi a/d ? cs5334 a/d ? cs5334 osc/pll table 3. provided data selection modes (pld version ab-x) digital audio source description s/pdif - cs8414 the cs8414 (u13) delivers the payload from an iec60958 (linear pcm) or iec61937 (nonlinear pcm) encoded bit-stream. the incoming s/pdif stream is connected to either j32 or j30. a/d - cs5334 the cs5334 (u25) delivers stereo pcm which has been encoded from the analog input signals on j55 and j56. pc a compressed digital audio stream is delivered in bursty format to the parallel port of the cs492x/cs493xx from a file on the pc. this transfer mode requires that the cdb4923/300 is in a parallel communication mode, and the parllply.exe program is then used to deliver com- pressed data through the pc interface. note : this data source is valid only for compressed audio and can be used only with parallel communication modes (i.e. intel or motorola mode). table 4. digital audio sources cdb4923 CDB49300 12 ds262db2 5.1.3 audio clocking the audio clocking scheme is illustrated below in figure 3. note that mclk is bidirectional with re- spect to the dsp. when the dsp is slaved to an ex- ternal mclk, i.e. the mclk source is not listed as dsp, the dsp will slave to the mclk of the cs8414 or the mclk derived from the on-board pll (u26) or the oscillator (y1). when the internal pll of the cs492x/cs493xx is being used, however, the dsp will master the mclk. caution must be observed when choosing a partic- ular data selection mode and configuring the dsp to ensure that there is no contention with the pld (u11). each pld mode given in table 3 lists the associated mclk master - this table should be ref- erenced whenever reconfiguring the cdb4923/300. a brief description of each mclk source is given in table 5. 5.2 external mode the external mode is designed to allow users to drive the dsp directly with an external micro- controller. stake headers j11 and j12 contain all of the signals required for host communication with the cs492x/cs493xx. when operating in this mode the dsp control pins are tri-stated by the pld (u11), effectively disabling the pc interface. consequently, the software bundled with the demo board will not be functional. the main dsp clock is always provided by the cdb4923/300 (please see the clocking section to determine how to select the oscillator or external pll), and the output signals audata0-2 are still routed to the cs8404a s/pdif transmitters and cs4340 dacs. depending on the external mode selected the user may be responsible for all data, control, and clock signals going to the dsp, or just control. note : all signals driven to the cs493xx must be +3.3 v logic. because the cs493xx does not have +5 v tolerant pads, an external buffer such as the 74vhc244 should be used for level conversion of any signals driv- en to the dsp. failure to buffer +5 v signals can cause permanent damage to the dsp. if necessary, level shifting buffers can be wired into the digital patch area of the CDB49300. mclk source description cs8414 the cs8414 (u13) derives the sampling fre- quency (fs) from an incoming s/pdif stream and masters a 256 fs mclk dsp the dsp (u1) masters mclk, generally when using broadcast application code osc/pll the source of the main dsp clock also sup- plies the system 256 fs mclk (see clocking for details) table 5. clocking descriptions cs5334 cs492x cs493xx cs8414 mclk cs8414 cs4340 cs4340 cs4340 cs8404a cs8404a cs8404a digital mclk / analog mclk dsp mclk osc pll dsp sclk dsp lrclk digital sclk / analog sclk digital lrclk / analog lrclk figure 3. audio clocking cdb4923 CDB49300 ds262db2 13 as mentioned above, many of the pld ? s i/o pins are tri-stated. the complete list of tri-stated pins for full external mode (pld mode 0) can be found in table 6. the complete list of tri-stated pins for external control mode (pld mode 1) can be found in table 7. by design, the clocking signals present at the mclk, lrclk, and sclk pins of the cs492x/cs493xx are used to drive both the audio input and output circuitry for the rest of the cdb4923/300 as shown in figure 3. this means that the s/pdif input, s/pdif output, analog out- put and analog input continue to function in the external modes. the user should only drive audio clocks in pld mode 0. pld mode 1 derives audio clocks from the cs8414. the three clocking configurations that the user should be aware of when using pld mode 0 are: dsp is slave to all audio clocks - user drives mclk/sclk/lrclk dsp masters lrclk/sclk - user drives mclk dsp masters mclk/lrclk/sclk - user drives no audio clocks only when the correct clocking is present on the 23mclk, 23lrclk, and 23sclk pins (j12), processed audio can be heard on the analog outputs (j13 - j20) and the digital outputs (j45 - j47). the analog outputs j13-j20 can be found in figure 12, and the digital outputs can be found in figure 13. the information in table 9 summarizes the opera- tion of switch s3. the table shows the data routing configuration, the mclk source, and the method of board control. this is intended as a quick refer- ence and can also be found in appendix j: switch summary . pin name pin number pin name pin number mclk 44 data0 17 cmpclk 28 data1 16 cmpreq 29 data2 15 cmpdat 27 data3 14 sclkn1 25 data4 11 slrclkn1 26 data5 10 sdatan1 22 data6 9 reset 36 data7 8 rd 5 a1, cdin 6 wr 4 a0, scclk 7 extmem 21 scpdio 19 cs 18 table 6. dsp pins tri-stated by u11 in pld mode 0 pin name pin number pin name pin number reset 36 data0 17 rd 5 data1 16 wr 4 data2 15 a1, cdin 6 data3 14 a0, scclk 7 data4 11 scpdio 19 data5 10 cs 18 data6 9 data7 8 table 7. dsp pins tri-stated by u11 in pld mode 1 mclk source description j12 the user must provide an oversampling clock on the 23mclk pin of stake header j12. ( note : this clock signal must be +3.3 v logic when using cs493xx) cs8414 the cs8414 (u13) derives the sampling fre- quency (fs) from an incoming s/pdif stream and masters a 256 fs mclk dsp the dsp (u1) masters mclk, generally when using broadcast application code table 8. clocking descriptions cdb4923 CDB49300 14 ds262db2 6. clocking there are four major clocks routed across the cdb4923/300: clkin for the dsp, mclk, lr- clk, and sclk. clkin is only used to drive the digital logic of the dsp core. mclk, lrclk, and sclk are used for synchronizing the audio sys- tems of the cdb4923/300. 6.1 dsp clock the dsp clock of the cs492x/cs493xx is provid- ed at the clkin pin (pin 30). the setting of jumper j1 (dsp clock) determines whether the cs492x/cs493xx uses the input clock as the dsp clock directly (clkin position) or uses the input clock as a reference for the internal pll (pll po- sition). there are two possible clock sources on the cdb4923/300. the first is the oscillator (y1). the second option is the external pll (u26) which can be configured to provide a processor clock ranging from 33 mhz to 81 mhz. all clock- ing circuitry can be found in figure 8. since the pll (u26) and the oscillator (y1) are co-dependent, only one can be used at any giv- en time. jumper j37 is used to select the source of the main dsp clock. it is vital to note that the jump- er j37 is a double jumper with two jumpers which must be moved in unison. if the jumpers are not moved together, board behavior will be unpredict- able. table 11 lists the oscillator requirements, and the two different settings for j37, where pins 3 and 4 are connected to the inputs of the pld. jumper j37 can also be found in figure 8. in order to use the 27 mhz oscillator directly, y1 should be populated with the 27 mhz oscillator in- cluded with the cdb4923/300 package. addition- pld mode data sel2 data sel1 data sel0 cs492x/cs493xx cmpdat cs492x/cs493xx sdatan1 mclk master control source 0 lo lo lo data and control lines accessed via j11 and j12 j12 or dsp j11 & j12 1 lo lo hi s/pdif -- cs8414 a/d -- cs5334 cs8414 j11 & j12 2 lo hi lo pc a/d -- cs5334 dsp pc 3 lo hi hi s/pdif -- cs8414 s/pdif -- cs8414 cs8414 pc 4 hi lo lo s/pdif -- cs8414 a/d -- cs5334 cs8414 pc 5 hi lo hi a/d -- cs5334 a/d -- cs5334 osc/pll pc 6 hi hi lo reserved 7 hi hi hi reserved table 9. data selection modes (switch s3, pld version ab-x) pld mode data_sel2 data_sel1 data_sel0 cs492x/cs493xx cmpdat cs492x/cs493xx sdatan1 mclk source 0 lo lo lo j12 j12 j12 or dsp 1hihihis/pdif ? cs8414 a/d -- cs5334 cs8414 table 10. external data selection modes (pld version ab-x) clock source y1 j37 - pin 3 j37 - pin 4 oscillator 27 mhz or 12.288 mhz oscillator osc osc external pll 27 mhz oscillator pll pll table 11. board clocking configurations (j37) cdb4923 CDB49300 ds262db2 15 ally, both jumpers of j37 should be set to the osc position. in this clocking configuration you should not use any modes which list osc/pll as the mclk source while y1 is 27 mhz. in order to use the 12.288 mhz oscillator directly, y1 should be populated with the 12.288 mhz os- cillator included with the cdb4923/300 package, and both jumpers of j37 should be set to the osc position. the 12.288 mhz oscillator can be used with those pld modes naming osc/pll as the mclk source, as 12.288 mhz is a standard 256fs oversampling frequency (256 * 48 khz). the choice of 12.288 mhz or 27 mhz is applica- tion code dependent. applications dealing with iec61937 packed compressed audio generally re- quire a 12.288 mhz input, while broadcast applica- tions typically require a 27 mhz input. check the relevant application code user ? s guide (an120- an123, an140 or an161-an163) for details on dsp clkin frequency. if the external pll is to be used, then y1 must be populated with a 27 mhz oscillator. the jumpers of j37 should both be placed in the pll position. the clkin pin of the dsp will now be driven with the processor clock (pclk) output of u26. the processor clock (pclk) output can be configured to generate either a many different frequencies, based upon the configuration of jumpers j67, j68, and j72 as listed in table 12. when using the external pll to generate the dsp clock, the clksel pin (j1) of the cs492x/cs493xx is typically set to ? ext clk ? . 6.2 mclk the system mclk on the cdb4923/300 can come from four different sources when using a provid- ed mode. some pld modes use the mclk gener- ated by the cs8414 s/pdif receiver (u13) when there is an incoming s/pdif stream. in pld mode 2, the dsp generates mclk when it is decoding a compressed bit stream delivered by the pc. some modes can select between an mclk which is sim- ply the frequency of the on-board oscillator (y1), or a programmable mclk generated by the exter- nal pll (u26). the source of mclk is dependent upon the pld mode and is indicated by the ? mclk source ? column of table 9 and table 24. u26 is a discrete pll which can generate many different audio frequencies in addition to the pro- cessor clock discussed above. the frequency of the audio clock is controlled by the states of the as1 and as0 pins which are set with jumpers j70 and j71. the available audio clock frequencies can be used to support many different sampling frequen- cies, depending on the desired mclk ratio. table 13 enumerates all possible mclk frequencies for the external pll. 6.3 lrclk and sclk lrclk and sclk are assumed to be generated by the dsp in all cases. the audio clocking diagram shown in figure 3, illustrates the clocking scheme of the cdb4923/300. if it is necessary to provide a complete slave mode for the dsp, please contact the factory for details on how to properly configure the cdb4923/300. pclk frequency j72 j67 j68 33.33 mhz lololo 54 mhz lo lo hi 66.66 mhz lo hi lo 80 mhz lo hi hi 32 mhz hi lo lo 81 mhz hi lo hi 50 mhz hi hi lo 40 mhz hihihi table 12. pclk configurations mclk frequency as1 (j70) as0 (j71) 24.576 mhz 1 1 12.288 mhz 0 0 11.2896 mhz 0 1 8.192 mhz 1 0 table 13. audio frequency selection (j58) cdb4923 CDB49300 16 ds262db2 7. input 7.1 analog input a stereo input is provided at rca jacks j55 and j56. these inputs are designed to accept a full-scale signal of 2 v rms . each single-ended signal is con- verted to a differential 2 v rms signal before being applied to the inputs of the cs5334 adc. the cs5334 and its analog input buffers can be found in figure 9. the cs5334 ? s clock signals can be accessed at the test points labeled alg_mclk, alg_sclk, and alg_lrclk (these test points can be found in figure 11). the serial data stream coming from the cs5334 can be probed at the 34sdata test point (tp22). jumper j52 is used to configure the cs5334 for slave or master mode. the default, slave mode, is used when the cs5334 accepts all clock signals from another source. when in master mode, the cs5334 accepts mclk and generates sclk and lrclk. the cdb4923/300 is config- ured to use the cs5334 in slave mode only . please contact the factory for details on how to use the cs5334 in master mode. the digital output format of the cs5334 can be configured with switch s4 as described in table 14. more details on the cs5334 can be found in the cs5334 datasheet. 7.2 digital input there are two possible sources of digital audio for the cdb4923/300: s/pdif, and bursty delivery from the host pc across the parallel interface. bursty delivery is accomplished by spooling a file from the host pc to the cdb4923/300 using the parllply.exe program found on the included floppy. audio delivered across the s/pdif inter- face comes from a digital source such as a dvd player. the s/pdif inputs are j30 (rca) and j32 (opti- cal), and can be found in figure 10. it is vital to note, though, that only one of these s/pdif inputs can be used at any given time. the active jack is de- termined by the setting of jumper j31 (s/pdif in). when j31 is in the ? opt ? position, s/pdif data will be accepted only from j32. when j31 is in the ? rca ? position, s/pdif data will be accepted only from j30. the s/pdif signal is routed to the cs8414 receiver (u13). the digital output format of the cs8414 is configured using switch s1 as described in table 15. the cdb4923/300 comes from the factory con- figured to operate in i 2 s mode. note that this de- fault should not be changed unless the dsp has been configured to use a different serial format. jumpers j65 and j66 control the sel and cs12/fck pins of the cs8414. these pins can be used to select what is displayed on the channel sta- tus outputs of the digital audio interface receiver. by default these pins are pulled up and the jumpers are not stuffed. if the user wishes to change the val- ues of these pins a stake header should be installed. the cs8414, its control switch, and jumpers can be found in figure 10. if more details on the cs8414 are needed, please reference the cs8414 datasheet. 34dif1 34dif0 digital input format lo lo 20-bit left justified, rising sclk lo hi 20-bit left justified, falling sclk hi lo 20 bit i 2 s, rising sclk (default) hi hi power down table 14. cs5334 digital output formats (s4) m2 m1 m0 audio serial port format lo lo lo out, l/r, 16-24 bits lo lo hi in, l/r, 16-24 bits lo hi lo out, l/r, i 2 s lo hi hi in, l/r, i 2 s (default) hi lo lo out, wsync, 16-24 bits hi lo hi out, l/r, 16 bits lsbj hi hi lo out, l/r, 18 bits lsbj hi hi hi out, l/r, msb last table 15. digital output format settings for cs8414 (s1) cdb4923 CDB49300 ds262db2 17 8. output 8.1 analog output the six discrete outputs provided on the cdb4923/300 are driven by cs4340 d/a convert- ers. they can be found at rca jacks j13-j16, j18, and j20. each output is driven directly by the cs4340 to provide a 3.5 v pp full scale output. the cs4340 and its control signals can be found in fig- ure 11, and the analog output buffers can be found in figure 12. the digital input format of the cs4340 is config- ured using switch s4. the cdb4923/300 is shipped with the cs4340 in i 2 s mode, and should not be changed unless the cs492x/cs493xx has been configured to use a different serial format. the list of data formats for the cs4340 can be found in table 16. for more details on the features of the cs4340, please reference the cs4340 datasheet. 8.2 analog output protection circuitry the cs4340 is designed to perform a ? soft ? ramp- ing of the bias voltage in order to prevent popping on the outputs. however, the series capacitance found in the analog buffers of the cs4340 require a finite amount of time to discharge when the cs4340 goes into reset (rc time constant). if the full reset period is not observed before new audio is delivered, popping can occur on the outputs. please see the cs4340 datasheet for more details. the four transistors connected to the mute output of each cs4340 are used to ensure that no 'popping' will occur on the outputs during power-up, power- down, and during audio clock discontinuities if the reset period is violated. 8.3 digital output the signals present on analog outputs j13-j16, j18, and j20 can also be found on the digital outputs j45-j47 (aoutdig0-aoutdig2). the optical transmitters are driven by cs8404a s/pdif trans- mitters (u19-21). the cs8404as are configured to operate in consumer mode by default. the mode of operation and status bits can be controlled by in- stalling a 16 pin header in j44 and placing jumpers on the signals that are to be programmed low. all signals on j44 are pulled up by default. the cs8404a transmitters and optical outputs can be found in figure 13. the digital input format of the s/pdif transmitters can be controlled with switch s2 as listed in table 17. more operational details for the cs8404a can be found in the cs8404a datasheet. optical transmitter j43 (xmt958) is directly con- nected to the s/pdif transmitter of the dsp. it can be used to directly observe the digital output of the cs492x/cs493xx when the application code run- ning on the part utilizes the transmitter. note that if the application code does not support s/pdif trans- mission, j43 will not generate valid data. please see the application note associated with the code in question (e.g. an120-123, an140, or an161- an163) to determine whether j43 should be active. 27dif1 27dif0 digital input format lo lo 16-24 bit i 2 s (default) lo hi 16-24 bit left justified hi lo 24-bit right justified hi hi 16-bit right justified table 16. cs4340 digital input formats (s4) m2 m1 m0 audio serial port format lo lo lo fsync & sck output lo lo hi left/right, 16-24 bits lo hi lo word sync, 16-24 bits lo hi hi reserved hi lo lo left/right, i 2 s (default) hi lo hi lsb justified, 16 bits hi hi lo lsb justified, 18 bits hi hi 1 msb last, 16-24 bits table 17. digital input format settings for cs8404a (s2) cdb4923 CDB49300 18 ds262db2 9. appendix a: schematics figure 4. cs492x/cs493xx cdb4923 CDB49300 ds262db2 19 figure 5. system power cdb4923 CDB49300 20 ds262db2 figure 6. pc interface cdb4923 CDB49300 ds262db2 21 figure 7. control logic cdb4923 CDB49300 22 ds262db2 figure 8. clocking cdb4923 CDB49300 ds262db2 23 figure 9. analog input cdb4923 CDB49300 24 ds262db2 figure 10. digital input cdb4923 CDB49300 ds262db2 25 figure 11. d/a converters cdb4923 CDB49300 26 ds262db2 figure 12. analog output cdb4923 CDB49300 ds262db2 27 figure 13. digital output cdb4923 CDB49300 28 ds262db2 figure 14. top layer cdb4923 CDB49300 ds262db2 29 figure 15. bottom layer cdb4923 CDB49300 30 ds262db2 figure 16. sstop cdb4923 CDB49300 ds262db2 31 figure 17. asystop cdb4923 CDB49300 32 ds262db2 figure 18. layer 2 cdb4923 CDB49300 ds262db2 33 figure 19. layer 3 cdb4923 CDB49300 34 ds262db2 10. appendix d: bill of materials item quan reference part number manufacturer description 1 15 c1,c7,c8,c9,c91,c96,c101,c129,c132,c15 9,c160,c163,c164,c167,c168 t491b105m035as kemet cap, 1uf, tant, 3528, 35v, 10% 2 42 c4,c10,c11,c12,c66,c67,c68,c69,c71,c72, c90,c95,c100,c106,c107,c108,c109,c110, c111,c112,c130,c133,c138,c139,c141,c14 3,c149,c150,c151,c152,c153,c157,c161,c 162,c165,c166,c169,c170,c172,c174,c175, c176 c1206c104k5rac kemet cap, .1uf, x7r, 1206, 50v, 10% 3 6 c18,c24,c28,c36,c41,c48 t491b335k020as kemet cap, 3.3uf, tant, 3528, 20v, 10% 4 12 c19,c20,c25,c26,c29,c30,c37,c38,c42,c4 3,c49,c50 c1206c152f5gac kemet cap, 1500pf, cog, 1206, 50v, 1% 5 3 c51,c55,c148 t491d476m020as kemet cap, 47uf, tant, 7343, 20v, 20% 6 5 c56,c156,c158,c171,c173 t491c476m010as kemet cap, 47uf, tant, 6032, 20v, 20% 7 1 c57 c1206c474k3rac kemet cap, .47uf, x7r, 1206, 25v, 10% 8 8 c58,c59,c60,c61,c62,c63,c64,c65 c1206c224k5rac kemet cap, .22uf, x7r, 1206, 50v, 10% 9 3 c73,c75,c76 c1206c103k5rac kemet cap, .01uf, x7r, 1206, 50v, 10% 10 1 c74 12062r683k9bb2 philips cap, .068uf, x7r, 1206, 50v, 10% 11 1 c113 1206cg471j9bb2 philips cap, 470pf, cog, 1206, 50v, 5% 12 3 c119,c122,c134 t491c106k020as kemet cap, 10uf, tant, 6032, 20v, 10% 13 2 c128,c120 c1206c100j5gac kemet cap, 10pf, cog, 1206, 50v, 5% 14 2 c131,c121 c1206c222j5gac kemet cap, 2200pf, cog, 1206, 50v, 5% 15 2 c140,c142 c1206c470j5gac kemet cap, 47pf, cog, 1206, 50v, 5% 16 1 c154 c340c225k5r5ca kemet cap, 2.2uf, x7r, c340, 50v, 10% 17 1 c155 c330c103k5r5ca kemet cap, .01uf, x7r, c330, 50v, 10% 18 5 d2,d3,d4,d5,d6 ln1351c-tr panasonic led, green, 3216 19 2 fb5,fb2 542-fb43-226 mouser inductor, ferrite bead 20 13 j1,j2,j3,j31,j52,j62,j63,j67,j68,j69,j70,j71 ,j72 tsw-103-07-g-s samtec stake header, 3x1, .1"center, gold 21 2 j11,j12 tsw-110-07-g-d samtec stake header, 10x2, .1"center, gold 22 1 j37 tsw-103-07-g-d samtec stake header, 3x2, .1" center, gold 23 1 j44 tsw-108-07-g-d samtec stake header, 8x2, .1" center, gold 24 4 j59,j60,j65,j66 tsw-102-07-g-s samtec stake header, 1x2, .1"center, gold 25 1 j64 tsw-111-07-g-s samtec stake header, 11x1, .1"center, gold 26 9 j13,j14,j15,j16,j18,j20,j30,j55,j56 16pj097 mouser connector, rca, ra, gold 27 1 j21 111-0110-001 johnson components binding post, blue 28 2 j24,j22 111-0103-001 johnson components binding post, black 29 1 j23 111-0102-001 johnson components binding post, red cdb4923 CDB49300 ds262db2 35 30 1 j57 111-0104-001 johnson components binding post, green 31 1 j29 747238-4 amp connector, d-sub, 25-pin, male, ra 32 1 j32 torx173 toshiba optical toslink reciever 33 4 j43,j45,j46,j47 totx173 toshiba optical transmitter 34 1 l1 43ls475 milller inductor, 47uf 35 3 q1,q5,q9 mmun2111lt1 motorola transistor, pnp, sot-23 36 3 q2,q6,q10 mmun2211lt1 motorola transistor, npn, sot-23 37 6 q3,q4,q7,q8,q11,q12 2sc2878 toshiba transistor, to-92 38 2 rp5,rp1 4610x-101-103 bourns res network, 10k-ohm, 10-pin, bussed 39 1 rp2 4606x-101-102 bourns res network, 1k-ohm, 6-pin, bussed 40 1 rp3 4610x-101-102 bourns res network, 1k-ohm, 10-pin, bussed 41 1 rp4 4606x-101-103 bourns res network, 10k-ohm, 6-pin, bussed 42 37 r1,r2,r49,r54,r59,r66,r74,r80,r112,r120 ,r150,r151,r152,r153,r160,r161,r163,r1 64,r184,r185,r186,r192,r193,r194,r212, r214,r216,r222,r224,r233,r235,r242,r24 8,r249,r256,r257,r258 crcw12061002ft dale res, 10k-ohm, 1206, 1%, 1/8w, metal film 43 3 r6,r196,r197 crcw1206472jt dale res, 4.7k-ohm,1206, 5%, 1/8w, metal film 44 38 r14,r17,r19,r24,r26,r28,r31,r34,r36,r4 1,r87,r88,r89,r90,r91,r92,r94,r96,r98,r 100,r102,r103,r104,r105,r106,r107,r110, r126,r129,r130,r131,r190,r191,r198,r20 0,r239,r240,r241 crcw1206330jt dale res, 33-ohm, 1206, 5%, 1/4w, metal film 45 6 r50,r55,r60,r67,r75,r81 crcw12065610ft dale res, 560-ohm, 1206, 1%, 1/4w, metal film 46 3 r84,r85,r226 crcw12061001ft dale res, 1k-ohm, 1206, 1%, 1/8w, metal film 47 5 r86,r210,r217,r220,r229 crcw1206151jt dale res, 150-ohm, 1206, 5%, 1/8w, metal film 48 5 r109,r119,r156,r169,r173 crcw1206000zp dale res, 0-ohm, 1206, 1%, 1/8w, metal film 49 2 r114,r225 crcw12062r0jt dale res, 2-ohm, 1206, 5%, 1/8w, metal film 50 1 r117 crcw12064750ft dale res, 470-ohm, 1206, 1%, 1/4w, metal film 51 1 r118 crcw1206750jt dale res, 75-ohm, 1206, 5%, 1/4w, metal film 52 1 r155 crcw12063320ft dale res, 330-ohm, 1206, 1%, 1/8w, metal film 53 4 r175,r187,r188,r189 crcw12061782ft dale res, 17.8k-ohm, 1206, 1%, 1/8w, metal film 54 4 r211,r221,r232,r247 crcw12064752ft dale res, 47k-ohm, 1206, 1%, 1/8w, metal film 55 2 r218,r228 crcw1206203jt dale res, 20k-ohm, 1206, 5%, 1/8w, metal film 56 1 r246 crcw12063302ft dale res, 33k-ohm, 1206, 1%, 1/8w, metal film 57 6 r250,r251,r252,r253,r254,r255 crcw1206202jt dale res, 2k-ohm, 1206, 5%, 1/4w, metal film 58 1 r259 crcw1206510jt dale res, 51-ohm, 1206, 5%, 1/4w, metal film item quan reference part number manufacturer description cdb4923 CDB49300 36 ds262db2 59 1 sw1 pt645tl50 c&k switch,pb,dpst,5 leg 60 3 s1,s2,s3 76sb03 grayhill dip switch, 3 position 61 1 s4 76sb04 grayhill dip switch, 4 position 62 14 tp5,tp17,tp18,tp19,tp20,tp21,tp22,tp23 ,tp24,tp25,tp26,tp27,tp28,tp29 tsw-101-07-g-s samtec stake header, 1x1, .1"center, gold 63 1 u1 cs493001-cl crystal 64 1 ux1 540-93-044-24-000 mill-max socket-d.u.t. hole, plcc-44, pih 65 1 u8 lm3940it-3.3 national semiconductor +3.3v regulator, to-220 66 2 u10,u9 dm74als541wm fairchild semiconductor ic,octal buffer/line driver/line reciever,so20 67 1 u11 epm7128alc84-12 altera integrated circuit, plcc84 68 1 ux11 540-99-084-24-000 mill-max socket, plcc-84, pih 69 1 u12 max708act maxim integrated circuit, supervisory cirquit, 70 1 u13 cs8414-cs crystal semi. integrated circuit, soic28 - wide 71 3 u16,u17,u18 cs4340-ks crystal integrated circuit, 24-bit, 96khz dac, 16pin soic 72 3 u19,u20,u21 cs8404a-cs crystal semiconductor integrated circuit, soic24 - wide 73 2 u23,u24 mc33078-p motorola integrated circuit, dual op amp, dip-8 74 2 ux23,ux24 110-93-308-41-001 mill-max s0cket, 300-mill, dip-8 75 1 u25 cs5334-ks crystal semiconductor integrated circuit, ssop20 76 1 u26 mk2744-10s micro-clock integrated circuit, 77 1 u27 lm2937et-2.5 national semiconductor voltage regulator, +2.5v, to-220 78 1 y1 cx21af-27.000mhz cal crystal oscilator,, 27.000mhz, ttl/cmos, dip-14 79 1 yx1 110-93-314-41-001 mill-max s0cket, 300-mill, dip-14 80 2 z1,z4 p6ke16a motorola diode, zener, axial, 13v, do-15 81 1 z2 p6ke6.8a motorola diode, zener, axial, 6.8v, do-7 82 5 j21,j22,j23,j24,j57 l1.50x.25tx.25t, ty pe e 24/19 squires binding post hook up wires 83 2 fb5,fb2 c2015l-1000-nd digi-key 24awg/hook-up/strned for ferrite beads 84 6 hardware 8f1943 newark standoffs 85 6 hardware hd343-nd digi-key screws, 4/40, 1/4" 86 1 pcb cdb4923/30 rev-a protech printed circuit board item quan reference part number manufacturer description cdb4923 CDB49300 ds262db2 37 11. appendix e: external memory schematics a11 a5 a12 a14 a8 a6 a11 a0 a7 a10 a8 a9 a[0:14] a1 a14 a13 a3 a9 a10 a2 a12 a13 a4 a1 a2 a3 a4 a5 a6 a7 a0 a1 a2 a3 a4 a5 a6 a7 a0 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d2 d1 d3 d4 d5 d6 d7 uc17 uc15 dsp15 a15 req23 emoe extmem uc17 uc16 a15 dsp15 emoe emoe emoe extmem mreset23 req23 uc16 uc15 uc17 +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v c3 .1uf u3 at27lv02 0a-90jc a7 5 a6 6 a5 7 a4 8 a3 9 a2 10 a1 11 a0 12 a17 30 a16 2 a15 3 a14 29 a13 28 a12 4 a11 25 a10 23 a09 26 a08 27 o0 13 o1 14 o2 15 o3 17 o4 18 o5 19 o6 20 o7 21 ce 22 oe 24 pgm 31 vpp 1 vcc 32 gnd 16 p1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 u5a 74lvc125 2 3 1 u5b 74lvc125 5 6 4 u5c 74lvc125 9 8 10 u5d 74lvc125 12 11 13 u5e 74lvc125 7 14 r1 10k r14 10k r13 10k u2 tc74vhc574fw q7 12 q6 13 q5 14 q4 15 q3 16 q2 17 q1 18 q0 19 ck 11 d0 2 d1 3 d2 4 d3 5 d4 6 d5 7 d6 8 d7 9 gnd 10 oe 1 vcc 20 u1 tc74vhc574fw q7 12 q6 13 q5 14 q4 15 q3 16 q2 17 q1 18 q0 19 ck 11 d0 2 d1 3 d2 4 d3 5 d4 6 d5 7 d6 8 d7 9 gnd 10 oe 1 vcc 20 c2 .1uf c1 .1uf c6 .1uf r10 0 uc16 3x1hdr 1 2 3 r9 0 uc15 3x1hdr 1 2 3 uc17 3x1hdr 1 2 3 r8 0 c5 .1uf + c7 47uf figure 20. crd4923-mem schematic cdb4923 CDB49300 38 ds262db2 #reset emad7 emad5 emad3 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a[16:0] a13 a0 a13 a0 a8 a3 a9 a1 a1 a4 a5 a4 a15 a2 a13 a10 a9 a9 a8 a6 a3 a7 a0 a5 a8 a12 a2 a15 a11 a6 a14 a12 a4 a14 a3 a6 a7 a10 a12 a11 a5 a7 a1 a14 a2 a10 a11 a16 emad7 emad2 emad1 emad0 emad2 emad6 emad4 emad5 emad1 emad[7:0] emad0 emad6 emad3 emad4 emad5 emad0 emad7 emad2 emad4 emad1 emad6 emad3 d5 d1 d3 d6 d6 d1 d2 d6 d3 d2 d7 d2 d5 d3 d5 d1 d4 d7 d0 d0 d4 d7 d0 d4 uc18 #aboot #extmem uc18 uc16 uc15 #emoe #emoe #emoe emad[7:0] uc15 uc17 #emoe #aboot #extmem #emwr #emwr uc17 #extmem uc16 uc18 #uc18 #emwr #uc18 #extmem emad[7:0] d[7:0] d[7:0] d[7:0] #emwr +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v c4 0.1uf c9 0.1uf c3 0.1uf u4 74lvc574 12 13 14 15 16 17 18 19 11 2 3 4 5 6 7 8 9 10 1 20 q7 q6 q5 q4 q3 q2 q1 q0 ck d0 d1 d2 d3 d4 d5 d6 d7 gnd oe vcc c1 0.1uf r13 49.9 c5 0.1uf r19 0 r12 49.9 r17 49.9 r18 49.9 u5 cy7c109v33 19 20 21 22 23 24 25 26 9 10 11 12 13 14 15 16 17 18 7 6 5 4 3 2 1 32 31 30 29 28 8 27 a1 a0 d0 d1 d2 gnd d3 d4 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a15 ce2 we a13 a8 a9 a11 oe a10 ce1 d7 d6 vcc d5 r15 49.9 r14 49.9 r11 49.9 c7 0.1uf r10 49.9 u3 74lvc574 12 13 14 15 16 17 18 19 11 2 3 4 5 6 7 8 9 10 1 20 q7 q6 q5 q4 q3 q2 q1 q0 ck d0 d1 d2 d3 d4 d5 d6 d7 gnd oe vcc + c6 47uf u2 74lvc574 12 13 14 15 16 17 18 19 11 2 3 4 5 6 7 8 9 10 1 20 q7 q6 q5 q4 q3 q2 q1 q0 ck d0 d1 d2 d3 d4 d5 d6 d7 gnd oe vcc r5 49.9 r3 49.9 r9 49.9 r7 49.9 u1 at27lv020a 5 6 7 8 9 10 11 12 30 2 3 29 28 4 25 23 26 27 13 14 15 17 18 19 20 21 22 24 31 1 32 16 a7 a6 a5 a4 a3 a2 a1 a0 a17 a16 a15 a14 a13 a12 a11 a10 a09 a08 o0 o1 o2 o3 o4 o5 o6 o7 ce oe pgm vpp vcc gnd r4 49.9 r8 49.9 r6 49.9 c8 0.1uf u6a 74lvc125 2 3 1 p1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 u6e 74lvc125 7 14 u6d 74lvc125 12 11 13 r2 10k r1 10k r16 10k u7 74vhc245 2 3 4 5 6 7 8 9 19 1 18 17 16 15 14 13 12 11 20 10 a1 a2 a3 a4 a5 a6 a7 a8 1g dir y1 y2 y3 y4 y5 y6 y7 y8 vcc gnd c2 0.1uf uuuu cdb4923 CDB49300 ds262db2 39 12. appendix f: board control software there is a suite of programs used to control the cdb4923/300. the definitions given refer to ? cdb30 ? executables which should be used with the both the cdb4923 and the cdb300. these software tools are designed to operate from a dos prompt and can work with any parallel port address (lpt1, lpt2, or lpt3). the default ad- dress for all of the programs is 0x378 (also known as lpt1), but the port address can be changed by using the '-p' option provided with every tool. each time a program is executed, the address that was used is echoed to the screen. if a program seem s to fail, verification of the parallel port address should the first step in troubleshooting. all of these programs are designed to access the cs492x/cs493xx using spi or i2c serial commu- nication, or intel or motorola parallel com- munication. the communication mode can be chosen from the command line with the '-m' option. it should be remembered that the mode chosen must correspond to the communication mode used by the cs492x/cs493xx. if the dsp is using a communication mode which does not match the software setting, results will be unpredictable. please see digital signal processor of this datasheet to learn how to change the dsp ? s com- munication mode. the source code for all programs can be found on the floppy disk provided with the cdb4923/300. these programs are documented and will provide insight into communicating successfully with the cs492x/cs493xx. the source for cdb30_ld is particularly useful since it demonstrates the full handshaking protocol required during boot-up of the cs492x/cs493xx. cdb30_ld - program used to load code into the cs492x/cs493xx. usage: cdb30_ld cdb4923 CDB49300 40 ds262db2 * = default examples: cdb23cmd 000001 -p3bc cdb23cmd -fac3.cfg -ms -p3bc cdb30_rd - program used to read back responses from the cs492x/cs493xx. if the intreq pin is not low when cdb30_rd is executed, the program will wait until intreq drops. press the ?enter? key to exit the read wait loop. usage: cdb30_rd [-pxxx] [-my] [-v] [-h] -p = parallel port address xxx = address (0x278, 378* or 3bc) -m = communication mode y = mode designator (i = i2c*, s = spi, m=mot, n=int) -v = disable verbose mode -h = this message * = default cdb30rst - program used to perform hard reset or soft reset on the cs492x/cs493xx. usage: cdb30rst [-s] [-pxxx] [-my] [-v] [-h] -s = soft reset -p = parallel port address xxx = address (0x278, 378* or 3bc) -m = communication mode y = mode designator (i = i2c*, s = spi, m=mot, n=int) -v = disable verbose mode -h = this message * = default parllply - program used to deliver compressed audio files to the parallel host port of the cs492x/cs493xx from the pc. usage: parllply cdb4923 CDB49300 ds262db2 41 -m = parallel control mode y = n (intel) or m (motorola)* -c = chunk size nnn = transfer size in words (252*) * = default cdb30_ad - program used to demonstrate autodetection on the cdb4923/300 only with iec61937 or iec60958 input. this program will download new application code from the pc each time a format change has been detected. the user should specify ? invalid ? for any application code or configuration file which does not exist. this program only allows serial control. usage: cdb30_ad cdb4923 CDB49300 42 ds262db2 13. appendix g: ic component listing by function 13.1 power u8 3.3 v voltage regulator {figure 5} u27 2.5 v voltage regulator {figure 5} 13.2 reset u12 max708 reset chip {figure 7} 13.3 clocking u26 mk2744 programmable phase locked loop (pll) {figure 8} y1 oscillator {figure 8} 13.4 signal routing/level conversion u11 epm7128e programmable logic device {figure 7} 13.5 dsp u1 cs492x/cs493xx multi-channel audio decoder {figure 4} 13.6 input u9 signal buffer for parallel port {figure 6} u10 signal buffer for parallel port {figure 6} u13 cs8414 s/pdif receiver {figure 10} u23 mc33078 analog input buffer {figure 9} u24 mc33078 analog input buffer {figure 9} u25 cs5334 20-bit a/d converter {figure 9} 13.7 output u16 cs4340 20-bit d/a converter {figure 11} u17 cs4340 20-bit d/a converter {figure 11} u18 cs4340 20-bit d/a converter {figure 11} u19 cs8404a s/pdif transmitter {figure 13} u20 cs8404a s/pdif transmitter {figure 13} u21 cs8404a s/pdif transmitter {figure 13} cdb4923 CDB49300 ds262db2 43 14. appendix h: jumpers listed by function 14.1 audio input jumpers j31 this jumper is used to select the input connector which is being used to receive s/pdif data. placing the jumper in the ? rca ? position enables the rca jack, and placing the jumper in the ? opt ? position enables the torx173 optical receiver. default: opt j52 this jumper is used to control the master/slave clocking mode of the cs5334 as described in the cs5334 datasheet. this jumper should be left in the ? slave ? position when using the fac- tory programmed pld provided with the cdb4923/300. default: slave j65 this jumper is used to control the sel pin of the cs8414. this pin, in conjunction with j66, is used to select which channel status pin information to display on the status output pins. please refer to the cs8414 datasheet for more details on how to configure the cs8414. default: hi (not populated). j66 this jumper is used to control the cs12/fck pin of the cs8414. this pin, in conjunction with j65, is used to select which channel status pin information to display on the status output pins. please refer to the cs8414 datasheet for more details on how to configure the cs8414. default: hi (not populated). 14.2 audio output jumpers j44 this particular component is actually a set of jumpers. each individual jumper can be used to control the state of one channel status bit in the outgoing s/pdif stream created by the cs8404a. more details can be found in the datasheet for the cs8404a and the specifications for iec60958 and iec61937 bitstreams. default: all bits hi {not populated} 14.3 dsp jumpers j1 this jumper is used to control the internal clocking of the cs492x/cs493xx. when in the ? clkin ? position, the cs492x/cs493xx uses the clock on the clkin pin to drive the dsp core directly. when in the ? pll ? position, the cs492x/cs493xx derives all internal clocks from the reference frequency provided at the clkin pin. default: clkin j2 this jumper selects the pull-up/pull-down state of the cs492x/cs493xx ? s wr pin. this jumper is used in conjunction with j3 and j62 to select the host interface mode of the cs492x/cs493xx when it comes out of reset. by default the cdb4923/300 is configured for i2c serial communication. the settings for j2 (wr ), j3 (rd ) and j62 (psel) are detailed in the cs4923/4/5/6/7/8/9 datasheet and the cs49300 datasheet. default: hi j3 this jumper selects the pull-up/pull-down state of the cs492x/cs493xx ? s rd pin. this jumper is used in conjunction with j2 and j62 to select the host interface mode of the cs492x/cs493xx when it comes out of reset. by default the cdb4923/300 is configured for i 2 c serial communication. the settings for j2 (wr ), j3 (rd ) and j62 (psel) are detailed in the cs4923/4/5/6/7/8/9 datasheet and the cs49300 datasheet. default: lo j11 stake header providing some serial communication lines, and all general purpose i/o pins. this header is also serves as the memory interface to the crd4923_mem/CDB49300_mem. this cdb4923 CDB49300 44 ds262db2 header can be used to probe signals during normal operation, and may be used as a wirewrap point when using data selection mode 0 or 1, as detailed in the data selection section of this datasheet. j12 stake header providing access to all serial audio data and clock pins. this header can be used to probe signals during normal operation, and may be used as a wirewrap point when using data selection mode 0 or 1, as detailed in the data selection section of this datasheet j62 this jumper selects the pull-up/pull-down state of the cs492x/cs493xx ? s psel pin. when coming out of reset, the state of the psel pin determines which parallel interface mode to use (motorola or intel) when initializing the cs492x/cs493xx into a parallel host interface mode. this jumper is used in conjunction with j2 and j3 to select the host interface mode of the cs492x/cs493xx when it comes out of reset. because the psel pin has multiplexed function- ality it also serves as scdio when in i 2 c mode. by default this jumper is in the ? hi ? position since the board is initially configured for i 2 c serial communication and the scdio pin is open-drained. the settings for j2 (wr ), j3 (rd ) and j62 (psel) are detailed in the cs4923/4/5/6/7/8/9 datasheet and the cs49300 datasheet. default: hi 14.4 power jumpers j59 this jumper connects dsp_pwr to the analog side of the cs492x/cs493xx. analog current con- sumption can be measured by removing this jumper and connecting an ammeter in series with the jumper. default: installed j60 this jumper connects dsp_pwr to the digital side of the cs492x/cs493xx. digital current consumption can be measured by removing this jumper and connecting an ammeter in series with the jumper. default: installed j63 this jumper is used to select the maximum voltage at which the i/o pins of the system pld (u11) will drive its outputs. the user can select between +3.3 v and +2.5 v. default: +3.3 v j69 this jumper (dsp_pwr) is used to select the core voltage for dsp power. this jumper is pro- vided to allow the user to evaluate both the cs4923/4/5/6/7/8 family and the cs49300 family of audio decoders. the cs4923/4/5/6/7/8 family requires +3.3 v, while the cs49300 family re- quires +2.5 v. the user can select between +3.3 v and +2.5 v. cdb4923 default: +3.3 v CDB49300 default: +2.5 v 14.5 system clocking jumpers j37 this dual position jumper select between an oscillator or the mk2744-10s discrete pll (u26) as the external clock source for the dsp of the cs492x/cs493xx, and it also selects the system mclk for non-s/pdif input modes. it is important to note the jumpers of j37 must move togeth- er. they must be both in the ? osc ? position or they must both be in the ? pll ? position. moving only one jumper will result in erratic behavior. when both jumpers are in the ? osc ? position, the cs492x/cs493xx clkin pin is driven by the oscillator, y1, and some of the data modes chosen by switch s3 will provide a system mclk which is also derived from y1. specifically, all data selection modes listed in table 9 and table 24 showing an mclk source of ? osc/pll ? will generate a system mclk equal to the frequency of the oscillator y1. if you have questions about how to utilize the external pll, please contact the factory before cdb4923 CDB49300 ds262db2 45 adjusting this jumper. y1 must be a 27 mhz oscillator before attempting to use u26. when both jumpers are in the ? pll ? position, u26 will drive the clkin pin of the cs492x/cs493xx with the configured pclk (refer to table 12 or table 22), and the system mclk will be driven by aclk. the frequency of mclk can be programmed by changing the values of the as1 and as0 pins of u26 as detailed in table 13 of this datasheet. default: osc osc j67 jumper used to set the value of the ps1 pin of u26. this jumper, in conjunction with j68 and j72, determines the processor clock frequency provided by the external pll. please refer to table 12 or table 22 for more details. default: lo j68 jumper used to set the values of the ps0 pin of u26. this jumper, in conjunction with j67 and j72, determines the processor clock frequency provided by the external pll. please refer to table 12 or table 22 for more details. default: hi j70 jumper used to set the values of the as1 pin of u26. this jumper, in conjunction with j71, de- termines the mclk frequency provided by the external pll. please refer to table 13 for more details. default: hi j71 jumper used to set the values of the as0 pin of u26. this jumper, in conjunction with j70, de- termines the mclk frequency provided by the external pll. please refer to table 13 for more details. default: 50 j72 jumper used to set the values of the ps2 pin of u26. this jumper, in conjunction with j67 and j68, determines the processor clock frequency provided by the external pll. please refer to table 12 or table 22 for more details. default: lo cdb4923 CDB49300 46 ds262db2 15. appendix i: jumpers listed by number note: each jumper listed below is described in appendix h: jumpers listed by function . the relevant section heading is listed beside each jumper name in braces {}. j1 cs492x/cs493xx dsp clock {dsp jumpers} default: clkin j2 cs492x/cs493xx wr pin {dsp jumpers} default: hi j3 cs492x/cs493xx rd pin {dsp jumpers} default: lo j11 stake header for cs492x/cs493xx & crd4923-mem & CDB49300-mem {dsp jumpers} j12 stake header for cs492x/cs493xx {dsp jumpers} j31 rca/optical s/pdif input selection {audio input jumpers} default: opt j37 oscillator/external pll select {system clocking jumpers} j44cs8404 channel status bits {audio output jumpers} default: all bits hi (not populated). j52 master/slave clocking mode of the cs5334 {audio input jumpers} default: slave j59 cs492x/cs493xx analog power {power jumpers} default: installed j60 cs492x/cs493xx digital power {power jumpers} default: installed j62 cs492x/cs493xx psel pin {dsp jumpers} default: hi j63 pld i/o power selection {power jumpers} default: +3.3 v j65 cs8414 sel pin {audio input jumpers} default: hi (not populated). j66 cs8414 cs12/fck pin. {audio input jumpers} default: hi (not populated). j67 ps1 pin of u26 {system clocking jumpers} default: lo j68 ps0 pin of u26 {system clocking jumpers} default: hi j69 dsp power selection {power jumpers} default: +2.5 v j70 as1 pin of u26 {system clocking jumpers} default: lo j71 as0 pin of u26 {system clocking jumpers} default: lo j72 ps2 pin of u26 {system clocking jumpers} default: lo cdb4923 CDB49300 ds262db2 47 16. appendix j: switch summary table 18 lists the jumper settings required for all four host interface modes of the cs492x/cs493xx. table 19 shows all of the digital output formats that can be selected for the cs5334 with switch s4. please see the cs5334 datasheet for a more de- tailed description of available digital output for- mats. table 20 shows all of the digital input formats that can be selected for the cs4340 with s4. please see the cs4340 datasheet for a more detailed descrip- tion of available digital input formats. table 21 shows all of the digital output formats that can be selected for the cs8414 with switch s1. please see the cs8414 datasheet for a more de- tailed description of available audio serial port for- mats. table 23 shows all of the digital input formats that can be selected for the cs8404a with switch s2. please see the cs8404a datasheet for a more de- tailed description of available digital input format. table 22. shows all available pll settings for the external pll on the cdb4923/4930. table 24 lists all possible data routing possibilities and the associated mclk source for the cdb4923/300. rd j3 wr j2 psel j62 host interface mode 011 serial i 2 c (psel == scdio) 10x serial spi 1 1 0 8-bit intel 1 1 1 8-bit motorola table 18. cs492x/cs493xx host interface mode selection 34dif1 34dif0 digital input format lo lo 20-bit left justified, rising sclk lo hi 20-bit left justified, falling sclk hi lo 20 bit i 2 s, rising sclk (default) hi hi power down table 19. cs5334 digital output formats (s4) 27dif1 27dif0 digital input format lo lo 16-24 bit i 2 s (default) lo hi 16-24 bit left justified hi lo 24-bit right justified hi hi 16-bit right justified table 20. cs4340 digital input formats (s4) m2 m1 m0 audio serial port format lo lo lo out, l/r, 16-24 bits lo lo hi in, l/r, 16-24 bits lo hi lo out, l/r, i 2 s compatible lo hi hi in, l/r, i 2 s (default) hi lo lo out, wsync, 16-24 bits hi lo hi out, l/r, 16 bits lsbj hi hi lo out, l/r, 18 bits lsbj hi hi hi out, l/r, msb last table 21. digital output format settings for cs8414 (s1) cdb4923 CDB49300 48 ds262db2 pclk frequency j72 j67 j68 33.33 mhz lo lo lo 54 mhz lo lo hi 66.66 mhz lo hi lo 80 mhz lo hi hi 32 mhz hi lo lo 81 mhz hi lo hi 50 mhz hi hi lo 40 mhz hihihi table 22. pclk configurations m2 m1 m0 audio serial port format lo lo lo fsync & sck output lo lo hi left/right, 16-24 bits lo hi lo word sync, 16-24 bits lo hi hi reserved hi lo lo left/right, i 2 s (default) hi lo hi lsb justified, 16 bits hi hi lo lsb justified, 18 bits hi hi hi msb last, 16-24 bits table 23. digital input format settings for cs8404a (s2) pld mode data sel2 data sel1 data sel0 cs492x/cs493xx cmpdat cs492x/cs493xx sdatan1 mclk master control source 0 lo lo lo data and control lines accessed via j11 and j12 j12 or dsp j11 & j12 1 lo lo hi s/pdif -- cs8414 a/d -- cs5334 cs8414 j11 & j12 2 lo hi lo pc a/d -- cs5334 dsp pc 3 lo hi hi s/pdif -- cs8414 s/pdif -- cs8414 cs8414 pc 4 hi lo lo s/pdif -- cs8414 a/d -- cs5334 cs8414 pc 5 hi lo hi a/d -- cs5334 a/d -- cs5334 osc/pll pc 6 hi hi lo reserved 7 hi hi hi reserved table 24. data selection modes (switch s3, pld version ab-x) ? notes ? |
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